HaRTES
 
The Project
Motivation  
Objectives  
 
Objectives

This project aims to develop an Ethernet switching infrastructure able to provide timeliness guarantees, efficient bandwidth usage and support for operational flexibility as required by dynamic real-time distributed embedded systems.

The project is build upon recent work on the FTT (Flexible Time-Triggered) communication paradigm to develop Ethernet switches with enhanced transmission control, traffic scheduling, service differentiation, transparent integration of non-real-time nodes and improved error confinement mechanisms, particularly with respect to temporal misbehaviors. The development work is being relied on FPGA technology.

The high level of operational flexibility with timeliness and safety guarantees provided by these switches represents a breakthrough in terms of the adequacy of switched Ethernet to emerging hard real-time applications that are adaptive and reactive to the environment yet open and integrated in large systems. The project will also consider related open standardization efforts such as ETHERNET-Powerlink and the AV Bridges and attempts will be made to contribute to them.


This main objective is broken down in three specific objectives:

1 - To include transmission control capabilities in Ethernet switches allowing the synchronization of parallel flows in different ports and the triggering of transmissions with low jitter;

2 - To integrate flexible scheduling and QoS management services inside an Ethernet switch with transmission control capabilities so that real-time communication objects can be added, removed or updated on-line, with timeliness guarantees;

3 – Implementation of traffic management features to separate different traffic classes at the input ports and handle them with mutual isolation, allowing the integration of ordinary Ethernet nodes, such as PCs with general-purpose operating systems, without jeopardizing the real-time properties.

 
 
 
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